Power transistors operate with heat losses. Since semiconductive materials are heat sensitive and semiconductive device parameters tend to vary significantly with temperature when they overheat, it is a common practice to mount power transistors to heat sinks. Typically, a transistor chip is mounted to a relatively large heat sink which is part of the transistor package. The heat sink of the package in turn, becomes mounted to a heat conductive radiator or dissipator such as a relatively large plate. In spite of the various heat sink provisions, power transistors operate at relatively high temperatures at which the outflowing heat equals the heat generated by the operation of the transistors.
In addition to operating at relatively high temperatures, the transistors are thermally cycled when they operate intermittently. Large transistors subjected to thermal cycling tend to fail by material fatigue. Common failure modes include such failures as cracking of chips, a separation of the leads from the chips or a separation of the chips from their heat removing substrates. Such problems indicate a desirability for mounting a semiconductor device chip in a package which readily transmits heat from the chip to an external heat sink. For such a device package to meet desired reliability standards, the package should also withstand thermal cycling, as well as prolonged operation at elevated tempertures.
In the past, power transistor chips, for example, have been mounted to heat sink headers by solder bonds. The problem with a chip bonded by a thin layer of solder to a heat conductive header has been one of stressing the bond and the chip as a result of an inherent mismatch between the thermal expansion coefficient of the transistor chip and that of its header. Typically, the heat conductive header is a relatively thick copper part. The coefficient of thermal expansion of copper, however, is different from that of the silicon material of the chip. Consequently, temperature changes in the package tend to cause stresses at the interface between the chip and its header.
The prior art also shows attempts related to improving the attachment of the external leads to the chip and to the header. Unitary lead frame-header structures offer advantages in the preparation of such structures prior to the assembly of chips to the structures. However, there are disadvantages in assembling the chips to such unitary structures. Each of the structures has leads which are already formed in place with respect to the header, and one of the chips has to be inserted between the leads and the header. There is a tendency to damage the chip at that point.
Also, since the header is desirably of a thicker stock than the leads, the headers are often chosen to be of a material stock different from that of the leads. It is therefore already known to assemble the relatively thinner leads to the relatively thicker header. One known method to assemble an initially two piece header-lead frame structure involves staking a collector lead to a heat sink header. Many of presently known transistor packages, however, retain problems which limit the lives of the transistors under actual operating conditions.
It is, therefore, an object to provide a thermally stable transistor package.
It is a further object to provide methods for assembling such a thermally stable transistor package.